1. Field of the Invention
The present invention relates to a test apparatus for judging whether an electronic device has a defect or not. More specifically, the invention relates to a test apparatus for testing an electronic device that outputs an output signal in which bits of output data to be outputted are inverted or non-inverted per cycle.
2. Related Art
Conventionally, a test of an electronic device (DUT) such as DRAM and SRAM for storing electronic data for example is carried out by comparing an output signal outputted out of the DUT in which preset electronic data is stored with an expected value pattern identical with the electronic data.
The implementation of multi-bit electronic device is also remarkably advancing lately. Therefore, a number of output pins of the DUT in which logic values of the signal to be outputted are inverted in the same time increases, causing noise in the output signals as a result. In order to reduce such noise, there is an electronic device that outputs the signal by inverting output data per cycle of the output signal. That is, when there are many output pins in which output data is inverted from the preceding cycle, the number of output pins is reduced by inverting and outputting the output data of the respective output pins. In this case, the DUT also outputs an inversion cycle signal indicating that the output signal of that cycle is inverted.
However, when the DUT inverts and outputs the data of the output signal as described above, an expected value pattern to be compared with that output signal must be also inverted.
However, the conventional test apparatus is unable to recognize whether or not the DUT has inverted the output signal. Therefore, in order to carry out the test, it has been necessary for a user who conducts the test to judge whether or not the output signal of the DUT is inverted corresponding to electronic data given to the DUT in advance and to prepare an expected value pattern corresponding to the judgment result. Accordingly, it has been difficult to carry out the test of the DUT efficiently.
Still more, in storing H fail data for a H-level expected value and L fail data for a L-level expected value in a fail memory as a result of the test of the DUT, the test apparatus ends up storing the fail data to be originally stored as the H fail data and L fail data as the L fail data and H fail data, respectively, when the output signal of the DUT and the expected value pattern are inverted. Therefore, it has been difficult to analyze the DUT in detail.